ARMv8 Register

Register Type

General purpose register

The amount of General purpose registers is 31 and divided into 4 groups

• Parameter Registers(X0-X7): Used as temporary registers or caller-saved register variables that can be used to save intermediate values within functions and between calls to other functions (8 registers can be used to pass arguments )
• Caller Saved Temporary Registers(X9-X15): If the caller calls another function with a value retained in any of these registers, the caller must save the affected registers on the stack in its own frame . They can be modified by the called subroutine without saving and restoring them before returning to the caller.
• Callee Saved Registers(X19-X29): These registers are saved in the callee frame. They can be modified by the callee of the subroutine, as long as they are saved and restored before returning.
• Special Purpose Register(X8,X16-X18,X29,X30):
• X8: It is an indirect result register, used to save the subroutine return address, try not to use it
• X16 and X17: temporary registers called within the program
• X18: Platform register, reserved for platform ABI, try not to use
• X29: Frame Pointer Register (FP)
• X30: Link register (LR)
• X31: stack pointer register SP or zero register ZXR

Neon and floating point registers

Special register

The amount of Special purpose registers is 32.

• Zero register(WZR,XZR): When the Zero register is read as a source register, a value of 0 will be obtained. When the Zero register is written as a destination register, the written value is discarded. The zero register can be used in most instructions (but not all instructions).
• Stack pointer (WSP, SP): In the ARMv8 architecture, each exception level has a stack pointer register, that is, it has 4 stack pointer registers. By default, the stack pointer register corresponding to exception level ELn is SP_ELn. For example, EL0 corresponds to SP_EL0, EL1 corresponds to SP_EL1, EL2 corresponds to SP_EL2, and EL3 corresponds to SP_EL3. When the execution state of the processor is AArch64 and is not at exception level EL0, you can use the dedicated 64-bit stack pointer (SP_ELn) related to the exception level and the stack pointer register (SP_EL0) related to the exception level EL0. EL0 can only access the SP_EL0 stack pointer register. The relationship between each exception level and the stack register pairs that can be used is shown in the figure below. Software can update the stack pointer to SP_EL0 by updating PSTATE.SP when executing at the target exception level. t indicates the use of the SP_EL0 stack pointer, h indicates the use of the SP_ELx stack pointer, and the t and h suffixes are based on the first letters of the thread and handler.
• Program Counter (PC): Early ARMv7 used general register R15 as a PC register. The PC made some clever programming tricks possible, but it made it difficult to design compilers and complex pipelines. Direct access to PC registers has been removed from the ARMv8 architecture, making return prediction easier and simplifying the ABI specification. PC registers are not accessed as named registers, but are accessed implicitly through certain instructions, such as PC-relative loads and generated addresses. The PC register cannot be explicitly used as the destination register for data processing instructions or load instructions.
• Exception Link Register (ELR): The ELR register stores the exception return address. ARMv8 defines three ELR registers, corresponding to exception levels EL1, EL2, and EL3.
• Saved Process Status Register (SPSR): When an exception occurs, the status of the processor will be saved to the relevant SPSR register. After an exception occurs, the processor will automatically save the contents of the PSTATE register to SPSR before handling the exception. When the exception returns, the processor state saved in SPSR will be restored to PSTATE. The SPSR register defined by ARMv8 is as follows. It is compatible with the SPSR register in ARMv7 and only uses the lower 32 bits.